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Low Power, 16-/24-Bit Sigma-Delta ADC AD7788/AD7789
FEATURES
AD7788: 16-bit resolution AD7789: 24-bit resolution Power Supply: 2.5 V to 5.25 V operation Normal: 75 A maximum Power-down: 1 A maximum RMS noise: 1.5 V AD7788: 16-bit p-p resolution AD7789: 19-bit p-p resolution (21.5 bits effective) Integral nonlinearity: 3.5 ppm typical Simultaneous 50 Hz and 60 Hz rejection Internal clock oscillator VDD monitor channel 10-lead MSOP
FUNCTIONAL BLOCK DIAGRAM
REFIN(+) REFIN(-) GND VDD
AD7788/ AD7789
AIN(+) AIN(-)
CLOCK DOUT/RDY DIN SCLK CS
- ADC*
SERIAL INTERFACE AND CONTROL LOGIC
*AD7788: 16-BIT ADC AD7789: 24-BIT ADC
03539-0-001
Figure 1.
GENERAL DESCRIPTION
The AD7788/AD7789 are low power, low noise, analog front ends for low frequency measurement applications. The AD7789 contains a low noise 24-bit - ADC with one differential input. The AD7788 is a 16-bit version of the AD7789. The device operates from an internal clock. Therefore, the user does not have to supply a clock source to the device. The output data rate is 16.6 Hz, which gives simultaneous 50 Hz/60 Hz rejection. The part operates with a single power supply from 2.5 V to 5.25 V. When operating from a 3 V supply, the power dissipation for the part is 225 W maximum. The AD7788/AD7789 is housed in a 10-lead MSOP.
INTERFACE
3-wire serial SPI(R), QSPITM, MICROWIRETM, and DSP compatible Schmitt trigger on SCLK
APPLICATIONS
Smart transmitters Battery applications Portable instrumentation Sensor measurement Temperature measurement Pressure measurement Weigh scales 4 to 20 mA loops
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD7788/AD7789 TABLE OF CONTENTS
AD7789--Specifications.................................................................. 3 AD7788--Specifications.................................................................. 4 AD7788/AD7789 Specifications..................................................... 5 Timing Characteristics..................................................................... 6 Absolute Maximum Ratings............................................................ 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 10 On-Chip Registers .......................................................................... 11 Communications Register (RS1, RS0 = 0, 0) ......................................................................... 11 Status Register (RS1, RS0 = 0, 0; Power-on/Reset = 0x88 [AD7788] and 0x8C [AD7789]).................................................................. 12 Mode Register (RS1, RS0 = 0, 1; Power-on/Reset = 0x02)............................... 12 Data Register (RS1, RS0 = 1, 1; Power-on/Reset = 0x0000 [AD7788] and 0x000000 [AD7789]) .......................................................... 13 ADC Circuit Information.............................................................. 14 Overview ..................................................................................... 14 Noise Performance ..................................................................... 14 Digital Interface .......................................................................... 14 Single Conversion Mode ....................................................... 15 Continuous Conversion Mode............................................. 15 Continuous Read Mode ........................................................ 16 Circuit Description......................................................................... 17 Analog Input Channel ............................................................... 17 Bipolar/Unipolar Configuration .............................................. 17 Data Output Coding .................................................................. 17 Reference Input........................................................................... 17 VDD Monitor ................................................................................ 18 Grounding and Layout .............................................................. 18 Outline Dimensions ....................................................................... 19
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD7788/AD7789 AD7789--SPECIFICATIONS1
Table 1. (VDD = 2.5 V to 5.25 V; REFIN(+) = 2.5 V; REFIN(-) = GND; GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.)
Parameter ADC CHANNEL SPECIFICATION Output Update Rate ADC CHANNEL No Missing Codes2 Resolution Output Noise Integral Nonlinearity Offset Error Offset Error Drift vs. Temperature Full-Scale Error3 Gain Drift vs. Temperature Power Supply Rejection ANALOG INPUTS Differential Input Voltage Ranges Absolute AIN Voltage Limits2 Analog Input Current Average Input Current2 Average Input Current Drift Normal Mode Rejection2 @ 50 Hz, 60 Hz Common Mode Rejection @ DC @ 50 Hz, 60 Hz2 REFERENCE INPUT REFIN Voltage Reference Voltage Range2 Absolute REFIN Voltage Limits2 Average Reference Input Current Average Reference Input Current Drift Normal Mode Rejection2 @ 50 Hz, 60 Hz Common Mode Rejection @ DC @ 50 Hz, 60 Hz AD7789B 16.6 24 19 1.5 15 3 10 10 0.5 90 REFIN GND - 30 mV VDD + 30 mV 400 50 65 90 100 2.5 0.1 V DD GND - 30 mV VDD + 30 mV 0.5 0.03 65 110 110 Unit Hz nom Bits min Bits p-p V rms typ ppm of FSR max V typ nV/C typ V typ ppm/C typ dB min V nom V min V max nA/V typ pA/V/C typ dB min dB min dB min V nom V min V max V min V max A/V typ nA/V/C typ dB min dB typ dB typ 50 1 Hz, 60 1 Hz AIN = 1 V 100 dB typ 50 1 Hz, 60 1 Hz REFIN = REFIN(+) - REFIN(-) Test Conditions/Comments
100 dB typ, AIN = 1 V REFIN = REFIN(+) - REFIN(-)
Input current varies with input voltage.
50 1 Hz, 60 1 Hz AIN = 1 V 50 1 Hz, 60 1 Hz
1 2 3
Temperature Range -40C to +105C. Specification is not production tested, but is supported by characterization data at initial product release. Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (VDD = 4 V).
Rev. 0 | Page 3 of 20
AD7788/AD7789 AD7788--SPECIFICATIONS1
Table 2. (VDD = 2.5 V to 5.25 V (B Grade); VDD = 2.7 V to 5.25 V (A Grade); REFIN(+) = 2.5 V; REFIN(-) = GND; GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.)
Parameter ADC CHANNEL SPECIFICATION Output Update Rate ADC CHANNEL No Missing Codes2 Resolution Output Noise Integral Nonlinearity Offset Error Offset Error Drift vs. Temperature Full-Scale Error3 Gain Drift vs. Temperature Power Supply Rejection ANALOG INPUTS Differential Input Voltage Ranges Absolute AIN Voltage Limits2 Analog Input Current Average Input Current2 Average Input Current Drift Normal Mode Rejection2 @ 50 Hz, 60 Hz Common Mode Rejection @ DC @ 50 Hz, 60 Hz2 REFERENCE INPUT REFIN Voltage Reference Voltage Range2 Absolute REFIN Voltage Limits2 Average Reference Input Current Average Reference Input Current Drift Normal Mode Rejection2 @ 50 Hz, 60 Hz Common Mode Rejection @ DC @ 50 Hz, 60 Hz AD7788A, B 16.6 16 16 1.5 15 50 3 10 10 0.5 90 90 REFIN GND - 30 mV VDD + 30 mV 400 50 65 60 90 90 100 100 2.5 0.1 VDD GND - 30 mV VDD + 30 mV 0.5 0.03 65 60 100 110 Unit Hz nom Bits min Bits p-p V rms typ ppm of FSR max ppm of FSR max V typ nV/C typ V typ ppm/C typ dB min dB typ V nom V min V max nA/V typ pA/V/C typ dB min dB min dB min dB typ dB min dB typ V nom V min V max V min V max A/V typ nA/V/C typ dB min dB min dB typ dB typ B Grade, 50 1 Hz, 60 1 Hz A Grade, 50 1 Hz, 60 1 Hz AIN = 1 V B Grade, 100 dB typ A Grade B Grade, 50 1 Hz, 60 1 Hz A Grade, 50 1 Hz, 60 1 Hz REFIN = REFIN(+) - REFIN(-) Test Conditions/Comments
B Grade A Grade
B Grade A Grade REFIN = REFIN(+) - REFIN(-)
Input current varies with input voltage.
B Grade, 50 1 Hz, 60 1 Hz A Grade AIN = 1 V 50 1 Hz, 60 1 Hz
1 2
Temperature Range: B Grade, -40C to +105C; A Grade, -40C to +85C. Specification is not production tested but is supported by characterization data at initial product release. 3 Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (VDD = 4 V).
Rev. 0 | Page 4 of 20
AD7788/AD7789 AD7788/AD7789 SPECIFICATIONS
Table 3.
Parameter LOGIC INPUTS All Inputs Except SCLK1 VINL, Input Low Voltage VINH, Input High Voltage SCLK Only (Schmitt-Triggered Input)1 VT(+) VT(-) VT(+) - VT(-) VT(+) VT(-) VT(+) - VT(-) Input Currents Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage1 VOL, Output Low Voltage1 VOH, Output High Voltage1 VOL, Output Low Voltage1 Floating-State Leakage Current Floating-State Output Capacitance Data Output Coding POWER REQUIREMENTS2 Power Supply Voltage VDD - GND Power Supply Currents IDD Current IDD (Power-Down Mode) AD7788A, B/ AD7789B Unit Test Conditions/Comments
0.8 0.4 2.0 1.4/2 0.8/1.4 0.3/0.85 0.9/2 0.4/1.1 0.3/0.85 1 10 VDD - 0.6 0.4 4 0.4 1 10 Offset Binary
V max V max V min V min/V max V min/V max V min/V max V min/V max V min/V max V min/V max A max pF typ V min V max V min V max A max pF typ
VDD = 5 V VDD = 3 V VDD = 3 V or 5 V VDD = 5 V VDD = 5 V VDD = 5 V VDD = 3 V VDD = 3 V VDD = 3 V VIN = VDD All Digital Inputs VDD = 3 V, ISOURCE = 100 A VDD = 3 V, ISINK = 100 A VDD = 5 V, ISOURCE = 200 A VDD = 5 V, ISINK = 1.6 mA
2.5/5.25 2.7/5.25 75 80 1
V min/max V min/max A max A max A max
AD7789, AD7788B Grade AD7788A Grade 65 A typ, VDD = 3.6 V 73 A typ, VDD = 5.25 V
1 2
Specification is not production tested but is supported by characterization data at initial product release. Digital inputs equal to VDD or GND.
Rev. 0 | Page 5 of 20
AD7788/AD7789 TIMING CHARACTERISTICS1, 2
Table 4. (VDD = 2.5 V to 5.25 V (AD7788B and AD7789), VDD = 2.7 V to 5.25 V (AD7788A); GND = 0 V, REFIN(+) = 2.5 V, REFIN(-) = GND, Input Logic 0 = 0 V, Input Logic 1 = VDD, unless otherwise noted.)
Parameter t3 t4 Read Operation t1 Limit at TMIN, TMAX (B Version) 100 100 0 60 80 0 60 80 10 80 100 10 0 30 25 0 Unit ns min ns min ns min ns max ns max ns min ns max ns max ns min ns max ns max ns min ns min ns min ns min ns min Conditions/Comments SCLK High Pulsewidth SCLK Low Pulsewidth CS Falling Edge to DOUT/RDY Active Time VDD = 4.75 V to 5.25 V VDD = 2.7 V to 3.6 V SCLK Active Edge to Data Valid Delay4 VDD = 4.75 V to 5.25 V VDD = 2.7 V to 3.6 V Bus Relinquish Time after CS Inactive Edge SCLK Inactive Edge to CS Inactive Edge SCLK Inactive Edge to DOUT/RDY High CS Falling Edge to SCLK Active Edge Setup Time4 Data Valid to SCLK Edge Setup Time Data Valid to SCLK Edge Hold Time CS Rising Edge to SCLK Edge Hold Time
t23
t55, 6 t6 t7 Write Operation t8 t9 t10 t11
1 2 3
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See Figure 3 and Figure 4. These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 SCLK active edge is falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.
Rev. 0 | Page 6 of 20
AD7788/AD7789
ISINK (1.6mA WITH VDD = 5V, 100A WITH VDD = 3V)
TO OUTPUT PIN 50pF
1.6V
ISOURCE (200A WITH VDD = 5V, 100A WITH VDD = 3V)
03539-0-002
Figure 2. Load Circuit for Timing Characterization
CS (I)
t1
DOUT/RDY (O) MSB LSB
t6 t5
t2 t3
SCLK (I)
t7
t4
I = INPUT, O = OUTPUT
03539-0-003
Figure 3. Read Cycle Timing Diagram
CS (I)
t8
SCLK (I)
t11
t9 t10
DIN (I) MSB I = INPUT, O = OUTPUT LSB
03539-0-004
Figure 4. Write Cycle Timing Diagram
Rev. 0 | Page 7 of 20
AD7788/AD7789 ABSOLUTE MAXIMUM RATINGS
Table 5. (TA= 25C, unless otherwise noted.)
Parameter VDD to GND Analog Input Voltage to GND Reference Input Voltage to GND Total AIN/REFIN Current (Indefinite) Digital Input Voltage to GND Digital Output Voltage to GND Operating Temperature Range B Grade A Grade Storage Temperature Range Maximum Junction Temperature MSOP JA Thermal Impedance JC Thermal Impedance Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature Rating -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V 30 mA -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +105C -40C to +85C -65C to +150C 150C 206C/W 44C/W 300C 220C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 8 of 20
AD7788/AD7789 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SCLK 1 CS 2 AIN(+) 3 REF(+) 5
03539-0-005
AD7788/ AD7789
10 9
DIN DOUT/RDY
8 VDD TOP VIEW AIN(-) 4 (Not to Scale) 7 GND 6
Pin No. 6
Mnemonic REFIN(-)
REF(-)
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 1 Mnemonic SCLK Function Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitttriggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the ADC in smaller batches of data. Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. Analog Input. AIN(+) is the positive terminal of the fully differential analog input. Analog Input. AIN(-) is the negative terminal of the fully differential analog input. Positive Reference Input. REFIN(+) can lie anywhere between VDD and GND + 0.1 V. The nominal reference voltage (REFIN(+) - REFIN(-)) is 2.5 V, but the part functions with a reference from 0.1 V to VDD.
7 8 9
GND VDD DOUT/RDY
2
CS
3 4 5
AIN(+) AIN(-) REFIN(+)
Function Negative Reference Input. This reference input can lie anywhere between GND and VDD - 0.1 V. Ground Reference Point. Supply Voltage, 3 V or 5 V Nominal. Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin will go high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. The end of a conversion is also indicated by the RDY bit in the status register. When CS is high, the DOUT/RDY pin is three-stated but the RDY bit remains active. Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers within the ADC, the register selection bits of the communications register identifying the appropriate register.
10
DIN
Rev. 0 | Page 9 of 20
AD7788/AD7789 TYPICAL PERFORMANCE CHARACTERISTICS
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 20 40 60 80 100 FREQUENCY (Hz) 120 140 160
8388591 0 VDD = 3V, VREF = 2.048V, TA = 25C, RMS NOISE = 1.25V 200 400 600 READ NO. 800 1000
03539-0-009
8388625
03539-0-007
Figure 6. Frequency Response with 16.6 Hz Update Rate
CODE
dB
Figure 8. AD7789 Noise Plot
70 60 50 40 30 20 10
VDD = 3V VREF = 2.048V TA = 25C RMS NOISE = 1.25V
3.0
2.5
VDD = 5V UPDATE RATE = 16.6Hz TA = 25C
RMS NOISE (V)
8388625
03539-0-008
OCCURENCE
2.0
1.5
1.0
0.5
0 8388591
0 0 0.5 1.0 1.5 2.0 2.5 3.0 VREF (V) 3.5 4.0 4.5 5.0
03539-0-013
CODE
Figure 7. AD7789 Noise Histogram
Figure 9. AD7788/AD7789 Noise vs. VREF
Rev. 0 | Page 10 of 20
AD7788/AD7789 ON-CHIP REGISTERS
The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated.
COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0)
The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communications register determines whether the next operation is a read or write operation, and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Table 7 outlines the bit designations for the communications register. CR0 through CR7 indicate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
CR7 WEN(0) CR6 0(0) CR5 RS1(0) CR4 RS0(0) CR3 R/W(0) CR2 CREAD(0) CR1 CH1(0) CR0 CH0(0)
Table 7. Communications Register Bit Designations
Bit Location CR7 Bit Name WEN Description Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually occurs. If a 1 is the first bit written, the part will not clock on to subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits will be loaded to the communications register. This bit must be programmed with a Logic 0 for correct operation. Register Address Bits. These address bits are used to select which of the ADC's registers are being selected during this serial interface communication. See Table 8. A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this position indicates that the next operation will be a read from the designated register. Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuously read, i.e., the contents of the data register are placed on the DOUT pin automatically when the SCLK pulses are applied. The communications register does not have to be written to for data reads. To enable continuous read mode, the instruction 001111XX must be written to the communications register. To exit the continuous read mode, the instruction 001110XX must be written to the communications register while the RDY pin is low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the instruction to exit continuous read mode. Additionally, a reset will occur if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device. These bits are used to select the analog input channel. The differential channel can be selected (AIN(+)/AIN(-)) or an internal short (AIN(-)/AIN(-)) can be selected. Alternatively, the power supply can be selected, i.e., the ADC can measure the voltage on the power supply, which is useful for monitoring power supply variation. The power supply voltage is divided by 5 and then applied to the modulator for conversion. The ADC uses a 1.17 V 5% on-chip reference as the reference source for the analog to digital conversion. Any change in channel resets the filter and a new conversion is started.
CR6 CR5-CR4 CR3 CR2
0 RS1-RS0 R/W CREAD
CR1-CR0
CH1-CH0
Table 8. Register Selection
RS1 0 0 0 1 1 RS0 0 0 1 0 1 Register Communications Register during a Write Operation Status Register during a Read Operation Mode Register Reserved Data Register Register Size 8-Bit 8-Bit 8-Bit 8-Bit 16-Bit (AD7788) 24-Bit (AD7789)
Table 9. Channel Selection
CH1 0 0 1 1 CH0 0 1 0 1 Channel AIN(+) - AIN(-) Reserved AIN(-) - AIN(-) VDD Monitor
Rev. 0 | Page 11 of 20
AD7788/AD7789
STATUS REGISTER (RS1, RS0 = 0, 0; POWER-ON/RESET = 0x88 [AD7788] AND 0x8C [AD7789])
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load bits RS1 and RS0 with 0. Table 10 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
SR7 RDY(1) SR6 ERR(0) SR5 0(0) SR4 0(0) SR3 1(1) SR2 WL(1/0) SR1 CH1(0) SR0 CH0(0)
Table 10. Status Register Bit Designations
Bit Location SR7 Bit Name RDY Description Ready bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register has been read or a period of time before the data register is updated with a new conversion result to indicate to the user not to read the conversion data. It is also set when the part is placed in powe-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange, underrange. Cleared by a write operation to start a conversion. This bit is automatically cleared. This bit is automatically cleared. This bit is automatically set. This bit is automatically cleared if the device is an AD7788 and it is automatically set if the device is an AD7789. This bit can be used to distinguish between the AD7788 and AD7789. These bits indicate which channel is being converted by the ADC.
SR6
ERR
SR5 SR4 SR3 SR2 SR1-SR0
0 0 1 1/0 CH1-CH0
MODE REGISTER (RS1, RS0 = 0, 1; POWER-ON/RESET = 0x02)
The mode register is an 8-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for range, unipolar or bipolar mode, enable or disable the buffer, or place the device into power-down mode. Table 11 outlines the bit designations for the mode register. MR0 through MR7 indicate the bit locations, MR denoting the bits are in the mode register. MR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter and sets the RDY bit.
MR7 MD1(0) MR6 MD0(0) MR5 0(0) MR4 0(0) MR3 0(0) MR2 U/B(0) MR1 1(1) MR0 0(0)
Table 11. Mode Register Bit Designations
Bit Location MR7-MR6 Bit Name MD1-MD0 Description Mode Select Bits. These bits select between continuous conversion mode, single conversion mode, and standby mode. In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. RDY goes low when a conversion is complete. The user can read these conversions by placing the device in continuous read mode whereby the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output the conversion by writing to the communications register. After power-on, the first conversion is available after a period 2/ fADC while subsequent conversions are available at a frequency of fADC. In single conversion mode, the ADC is placed in power-down mode when conversions are not being performed. When single conversion mode is selected, the ADC powers up and performs a single conversion, which occurs after a period 2/fADC. The conversion result in placed in the data register, RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register and RDY remains active (low) until the data is read or another conversion is performed. See Table 12.
Rev. 0 | Page 12 of 20
AD7788/AD7789
Bit Location MR5-MR3 MR2 Bit Name 0 U/B Description This bit must be programmed with a Logic 0 for correct operation. Unipolar/Bipolar Bit. Set by user to enable unipolar coding, i.e., zero differential input will result in 000...000 output and a full-scale differential input will result in 111...111 output. Cleared by the user to enable bipolar coding. Negative full-scale differential input will result in an output code of 000...000, zero differential input will result in an output code of 100...000, and a positive full-scale differential input will result in an output code of 111...111. This bit must be programmed with a Logic 1 for correct operation. This bit must be programmed with a Logic 0 for correct operation.
MR1 MR0
1 0
Table 12. Operating Modes
MD1 0 0 1 1 MD0 0 1 0 1 Mode Continuous Conversion Mode (Default) Reserved Single Conversion Mode Powerdown Mode
DATA REGISTER (RS1, RS0 = 1, 1; POWER-ON/RESET = 0x0000 [AD7788] AND 0x000000 [AD7789])
The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from this register, the RDY bit/pin is set.
Rev. 0 | Page 13 of 20
AD7788/AD7789 ADC CIRCUIT INFORMATION
OVERVIEW
The AD7788/AD7789 is a low power ADC that incorporates a - modulator and on-chip digital filtering intended for the measurement of wide dynamic range, low frequency signals such as those in pressure transducers, weigh scales, and temperature measurement applications. The part has one unbuffered differential input. The device requires an external reference voltage between 0.1 V and VDD. Figure 10 shows the basic connections required to operate the part.
POWER SUPPLY 0.1F 10F
DIGITAL INTERFACE
As previously outlined, the AD7788/AD7789's programmable functions are controlled using a set of on-chip registers. Data is written to these registers via the part's serial interface and read access to the on-chip registers is also provided by this interface. All communications with the part must start with a write to the communications register. After power-on or reset, the device expects a write to its communications register. The data written to this register determines whether the next operation is a read operation or a write operation and also determines to which register this read or write operation occurs. Therefore, write access to any of the other registers on the part begins with a write operation to the communications register followed by a write to the selected register. A read operation from any other register (except when continuous read mode is selected) starts with a write to the communications register followed by a read operation from the selected register. The AD7788/AD7789's serial interface consists of four signals: CS, DIN, SCLK, and DOUT/RDY. The DIN line is used to transfer data into the on-chip registers while DOUT/RDY is used for accessing from the on-chip registers. SCLK is the serial clock input for the device and all data transfers (either on DIN or DOUT/RDY) occur with respect to the SCLK signal. The DOUT/ RDY pin operates as a Data Ready signal also, the line going low when a new data-word is available in the output register. It is reset high when a read operation from the data register is complete. It also goes high prior to the updating of the data register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. CS is used to select a device. It can be used to decode the AD7788/AD7789 in systems where several components are connected to the serial bus. Figure 3 and Figure 4 show timing diagrams for interfacing to the AD7788/AD7789 with CS being used to decode the part. Figure 3 shows the timing for a read operation from the AD7788/AD7789's output shift register while Figure 4 shows the timing for a write operation to the input shift register. In all modes except continuous read mode, it is possible to read the same word from the data register several times even though the DOUT/RDY line returns high after the first read operation. However, care must be taken to ensure that the read operations have been completed before the next output update occurs. In continuous read mode, the data register can be read only once.
VDD REFIN(+) IN+ OUT- OUT+
AD7788/ AD7789
AIN(+) AIN(-) REFIN(-) GND
03539-0-006
CS DOUT/RDY SCLK MICROCONTROLLER
IN-
Figure 10. Basic Connection Diagram
The output rate of the AD7788/AD7789 (fADC) is 16.6 Hz with the settling time equal to 2 x tADC (120.4 ms). Normal mode rejection is the major function of the digital filter. Simultaneous 50 Hz and 60 Hz rejection is optimized as notches are placed at both 50 Hz and 60 Hz with this update rate (see Figure 6).
NOISE PERFORMANCE
The AD7788/AD7789 has an rms noise of 1.5 V rms typically, which corresponds to a peak-to-peak resolution of 16 bits for the AD7788 and 19 bits (equivalent to an effective resolution of 21.5 bits) for the AD7789. The numbers given are for the bipolar input range with a reference of 2.5 V. The noise was measured with a differential input voltage of 0 V. The peak-topeak resolution figures represent the resolution for which there will be no code flicker within a six-sigma limit. The output noise comes from two sources. The first is the electrical noise in the semiconductor devices (device noise) used in the implementation of the modulator. The second is quantization noise, which is added when the analog input is converted into the digital domain.
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AD7788/AD7789
The serial interface can operate in 3-wire mode by tying CS low. In this case, the SCLK, DIN, and DOUT/RDY lines are used to communicate with the AD7788/AD7789. The end of conversion can be monitored using the RDY bit in the status register. This scheme is suitable for interfacing to microcontrollers. If CS is required as a decoding signal, it can be generated from a port pin. For microcontroller interfaces, it is recommended that SCLK idles high between data transfers. The AD7788/AD7789 can be operated with CS being used as a frame synchronization signal. This scheme is useful for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by CS since CS would normally occur after the falling edge of SCLK in DSPs. The SCLK can continue to run between data transfers, provided the timing numbers are obeyed. The serial interface can be reset by writing a series of 1s on the DIN input. If a Logic 1 is written to the AD7788/AD7789 line for at least 32 serial clock cycles, the serial interface is reset. This ensures that in 3-wire systems, the interface can be reset to a known state if the interface gets lost due to a software error or some glitch in the system. Reset returns the interface to the state in which it is expecting a write to the communications register. This operation resets the contents of all registers to their poweron values. The AD7788/AD7789 can be configured to continuously convert or to perform a single conversion. See Figure 11 through Figure 13.
Single Conversion Mode
In single conversion mode, the AD7788/AD7789 is placed in shutdown mode between conversions. When a single conversion is initiated by setting MD1 to 1 and MD0 to 0 in the mode register, the AD7788/AD7789 powers up, performs a single conversion, and then returns to shutdown mode. A conversion will require a time period of 2 x tADC. DOUT/RDY goes low to indicate the completion of a conversion. When the data-word has been read from the data register, DOUT/RDY will go high. If CS is low, DOUT/RDY will remain high until another conversion is initiated and completed. The data register can be read several times, if required, even when DOUT/ RDY has gone high.
Continuous Conversion Mode
This is the default power-up mode. The AD7788/AD7789 will continuously convert, the RDY pin in the status register going low each time a conversion is complete. If CS is low, the DOUT/RDY line will also go low when a conversion is complete. To read a conversion, the user can write to the communications register, indicating that the next operation is a read of the data register. The digital conversion will be placed on the DOUT/RDY pin as soon as SCLK pulses are applied to the ADC. DOUT/RDY will return high when the conversion is read. The user can read this register additional times, if required. However, the user must ensure that the data register is not being accessed at the completion of the next conversion or else the new conversion word will be lost.
CS
DIN
0x10
0x82
0x10
0x82
DOUT/RDY
DATA
DATA
SCLK
03539-0-010
Figure 11. Single Conversion
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AD7788/AD7789
Continuous Read Mode
Rather than write to the communications register each time a conversion is complete to access the data, the AD7788/AD7789 can be placed in continuous read mode. By writing 001111XX to the communications register, the user needs only to apply the appropriate number of SCLK cycles to the ADC and the data word will automatically be placed on the DOUT/RDY line when a conversion is complete. When DOUT/RDY goes low to indicate the end of a conversion, sufficient SCLK cycles must be applied to the ADC and the data conversion will be placed on the DOUT/RDY line. When the conversion is read, DOUT/RDY will return high until the next conversion is available. In this mode, the data can be read only once. Also, the user must ensure that the data-word is read before the next conversion is complete. If the user has not read the conversion before the completion of the next conversion or if insufficient serial clocks are applied to the AD7788/AD7789 to read the word, the serial output register is reset when the next conversion is complete and the new conversion is placed in the output serial register. To exit the continuous read mode, the instruction 001110XX must be written to the communications register while the RDY pin is low. While in the continuous read mode, the ADC monitors activity on the DIN line so that it can receive the instruction to exit the continuous read mode. Additionally, a reset will occur if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device.
CS
0x38 DIN
0x38
DOUT/RDY
DATA
DATA
SCLK
03539-0-012
Figure 12. Continuous Conversion
CS
DIN
0x3C
DOUT/RDY
DATA
DATA
DATA
SCLK
03539-0-011
Figure 13. Continuous Read
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AD7788/AD7789 CIRCUIT DESCRIPTION
ANALOG INPUT CHANNEL
The AD7788/AD7789 has one differential analog input channel that is connected to the modulator, i.e., the input is unbuffered. Note that this unbuffered input path provides a dynamic load to the driving source. Therefore, resistor/capacitor combinations on the input pins can cause dc gain errors, depending on the output impedance of the source that is driving the ADC input. Table 13 shows the allowable external resistance/capacitance values such that no gain error at the 16-bit level is introduced (AD7788), while Table 14 shows the allowable external resistance/capacitance values such that no gain error at the 20-bit level is introduced (AD7789). Table 13. External R-C Combination for No 16-Bit Gain Error (AD7788)
C (pF) 50 100 500 1000 5000 R () 22.8K 13.1K 3.3K 1.8K 360
the analog input range on the AIN(+) input is 0 V to 5 V. The bipolar/unipolar option is chosen by programming the B/U bit in the mode register.
DATA OUTPUT CODING
When the ADC is configured for unipolar operation, the output code is natural (straight) binary with a zero differential input voltage resulting in a code of 00...00, a midscale voltage resulting in a code of 100...000, and a full-scale input voltage resulting in a code of 111...111. The output code for any analog input voltage can be represented as Code = 2N x (AIN/VREF) When the ADC is configured for bipolar operation, the output code is offset binary with a negative full-scale voltage resulting in a code of 000...000, a zero differential input voltage resulting in a code of 100...000, and a positive full-scale input voltage resulting in a code of 111...111. The output code for any analog input voltage can be represented as Code = 2N - 1 x [(AIN/VREF) + 1] where AIN is the analog input voltage and N = 16 for the AD7788 and 24 for the AD7789.
Table 14. External R-C Combination for No 20-Bit Gain Error (AD7789)
C (pF) 50 100 500 1000 5000 R () 16.7K 9.6K 2.2K 1.1K 160
REFERENCE INPUT
The AD7788/AD7789 has a fully differential input capability for the channel. The common-mode range for these differential inputs is from GND to VDD. The reference input is unbuffered and, therefore, excessive R-C source impedances will introduce gain errors. The reference voltage REFIN (REFIN(+) - REFIN(-)) is 2.5 V nominal, but the AD7788/AD7789 is functional with reference voltages from 0.1 V to VDD. In applications where the excitation (voltage or current) for the transducer on the analog input also drives the reference voltage for the part, the effect of the low frequency noise in the excitation source will be removed because the application is ratiometric. If the AD7788/AD7789 is used in a nonratiometric application, a low noise reference should be used. Recommended 2.5 V reference voltage sources for the AD7788/ AD7789 include the ADR381 and ADR391, which are low noise, low power references. If the analog circuitry uses a 2.5 V power supply, the reference voltage source will require some headroom. In this case, a 2.048 V reference such as the ADR380 or ADR390 can be used. Again, these are low power, low noise references. Also note that the reference inputs provide a high impedance, dynamic load. Because the input impedance of each reference input is dynamic, resistor/capacitor combinations on these inputs can cause dc gain errors, depending on the output impedance of the source that is driving the reference inputs.
The absolute input voltage includes the range between GND - 30 mV and VDD + 30 mV. The negative absolute input voltage limit does allow the possibility of monitoring small true bipolar signals with respect to GND. The absolute input voltage includes the range between GND - 30 mV and VDD + 30 mV. The negative absolute input voltage limit does allow the possibility of monitoring small true bipolar signals with respect to GND.
BIPOLAR/UNIPOLAR CONFIGURATION
The analog input to the AD7788/AD7789 can accept either unipolar or bipolar input voltage ranges. A bipolar input range does not imply that the part can tolerate large negative voltages with respect to system GND. Unipolar and bipolar signals on the AIN(+) input are referenced to the voltage on the AIN(-) input. For example, if AIN(-) is 2.5 V and the ADC is configured for unipolar mode, the input voltage range on the AIN(+) pin is 2.5 V to 5 V. If the ADC is configured for bipolar mode,
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AD7788/AD7789
Reference voltage sources like those recommended above (e.g., ADR391) will typically have low output impedances and are, therefore, tolerant to having decoupling capacitors on REFIN(+) without introducing gain errors in the system. Deriving the reference input voltage across an external resistor will mean that the reference input sees a significant external source impedance. External decoupling on the REFIN pins would not be recommended in this type of circuit configuration. The printed circuit board that houses the AD7788/AD7789 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. A minimum etch technique is generally best for ground planes because it gives the best shielding. It is recommended that the AD7788/AD7789's GND pin be tied to the AGND plane of the system. In any layout, it is important that the user keep in mind the flow of currents in the system, ensuring that the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. Avoid forcing digital currents to flow through the AGND sections of the layout. The AD7788/AD7789's ground plane should be allowed to run under the AD7788/AD7789 to prevent noise coupling. The power supply lines to the AD7788/AD7789 should use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best, but it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. Good decoupling is important when using high resolution ADCs. VDD should be decoupled with 10 F tantalum in parallel with 0.1 F capacitors to GND. To achieve the best from these decoupling components, they should be placed as close as possible to the device, ideally right up against the device. All logic chips should be decoupled with 0.1 F ceramic capacitors to DGND.
VDD MONITOR
Along with converting external voltages, the analog input channel can be used to monitor the voltage on the VDD pin. When the CH1 and CH0 bits in the communications register are set to 1, the voltage on the VDD pin is internally attenuated by 5 and the resultant voltage is applied to the - modulator using an internal 1.17 V reference for analog to digital conversion. This is useful because variations in the power supply voltage can be monitored.
GROUNDING AND LAYOUT
Since the analog inputs and reference inputs of the ADC are differential, most of the voltages in the analog modulator are common-mode voltages. The excellent common-mode rejection of the part will remove common-mode noise on these inputs. The digital filter will provide rejection of broadband noise on the power supply, except at integer multiples of the modulator sampling frequency. The digital filter also removes noise from the analog and reference inputs, provided that these noise sources do not saturate the analog modulator. As a result, the AD7788/AD7789 is more immune to noise interference than a conventional high resolution converter. However, because the resolution of the AD7788/AD7789 is so high, and the noise levels from the AD7788/AD7789 are so low, care must be taken with regard to grounding and layout.
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AD7788/AD7789 OUTLINE DIMENSIONS
3.00 BSC
10
6
3.00 BSC
1 5
4.90 BSC
PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.00 0.27 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA 1.10 MAX 8 0 0.80 0.60 0.40
SEATING PLANE
0.23 0.08
Figure 14. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Table 15. Ordering Guide
Model AD7788BRM AD7788BRM-REEL AD7788ARM AD7788ARM-REEL AD7789BRM AD7789BRM-REEL Temperature Range -40C to +105C -40C to +105C -40C to +85C -40C to +85C -40C to +105C -40C to +105C Package Description 10-Lead Mini Small Outline Package (MSOP) 10-Lead Mini Small Outline Package (MSOP) 10-Lead Mini Small Outline Package (MSOP) 10-Lead Mini Small Outline Package (MSOP) 10-Lead Mini Small Outline Package (MSOP) 10-Lead Mini Small Outline Package (MSOP) Package Option RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 Branding COX COX COZ COZ COY COY
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AD7788/AD7789 NOTES
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. C03539-0-8/03(0)
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